Can RISC-V surpass X86 and ARM?

In the previous article, we introduced X86 and ARM. X86 is based on the CISC architecture and currently dominates the PC and server domain; ARM, which is based on the RISC architecture, leads by a large margin in the mobile domain, such as your smartphones and tablets.

However, more and more companies are becoming attracted to RISC-V. For example, tech giants like Google have recognized the potential of RISC-V and announced that Android 15 would officially support microprocessors with the RISC-V architecture.

RISC-V International Members

RISC-V and ARM share the RISC architecture. Why are so many companies joining the RISC-V Community Organization?

Why do many people say RISC-V is potentially the biggest competitor to ARM and may reshape the landscape of the computing field?

In this article, we will explore exactly what RISC-V is, its advantages over ARM and x86, what issues it faces, and how it may develop in the future.

Introduction

RISC-V, fully known as "Reduced Instruction Set Computing V", where "Reduced Instruction Set Computing" refers to a simplified set of computing commands, and "V" refers to the fifth generation.

RISC originates from the Berkeley RISC project led by Turing Award winner David Patterson at the University of California, Berkeley in 1980. The first generation of RISC-I processor it designed contained only 32 instructions and half as many transistors as contemporaneous CISC design chips, yet outperformed any other chip of that era, showcasing immense power.

By the mid to late 1980s, RISC chips were enjoying a boom. Companies like HP and SUN began to release machines equipped with RISC chips, including workstations and servers. The success of SUN's SPARC system highlighted the potential of RISC. IBM also joined the RISC project, with its Power series CPUs deployed over the next 30 years incorporating the RISC architecture.

In 2010, a research team at the University of California, Berkeley, simply wanted an instruction set that could better serve teaching. They considered ARM, SPARC, and X86 but found these instruction sets not only complex but also plagued by IP law issues, authorization difficulties, and costly licensing fees. As a result, they decided to spearhead a brand-new open-source instruction set architecture project—RISC-V was born.

Interestingly, great events in history often emerge unintentionally. Thanks to its simplicity, efficiency, low energy consumption, modularity, extensibility, free access, and lack of legacy inefficiencies, RISC-V quickly garnered wide appeal. Upon realizing its value, the RISC-V team decided to bring it to market.

In 2015, the RISC-V Foundation was established, leveraging completely open-source code unhindered by patent restrictions, backed up by a BSD license—one of the most beloved open-source licenses among commercial companies. In June 2019, David Patterson, one of the founders of the RISC-V Foundation, announced the plan to set up a RISC-V international open-source laboratory within the Tsinghua-Berkeley Shenzhen Institute. In March 2020, the RISC-V Foundation relocated its headquarters to Switzerland and was renamed RISC-V International to avoid U.S. trade restrictions on China.

Architecture Overview

By far, there have been a plethora of CPU architectures, such as X86, ARM, RISC-V, MIPS, and so on. Though numerous, they can logically be divided into two types: Complex Instruction Set and Reduced Instruction Set.

The representative of the Complex Instruction Set is X86, led by Intel and AMD, and this type equips nearly all of our computers.

The representative of the Reduced Instruction Set is ARM. Apple has greatly contributed to the prevalence of ARM in the mobile sector. Early on, when Apple approached Intel hoping that it could develop a high-performance mobile chip specifically for the iPhone, Intel missed the opportunity. As a result, Apple turned its attention to the ARM instruction set.

Thanks to the outstanding energy-efficiency ratio of the Reduced Instruction Set, Apple has now completely ditched the X86 and started using self-developed M series chips using the ARM instruction set across the entire Mac range.

What is an instruction set, exactly? Is the Complex Instruction Set, which is even disliked by Apple, necessarily inferior to a simplified one?

We can imagine hardware as a newly built residential area and software as the supporting facilities around the area, such as hospitals and supermarkets. There's a river between the small area and the surrounding facilities. If they want to connect seamlessly, they need the instruction set to act as a bridge. Both the Complex and Reduced Instruction Sets can connect the two places, but the purpose from one place to another can differ. For example, if Xiao Ming has a motorcycle, he can quickly get to the supermarket across the bridge from the residential area to buy water, but if he needs to transport a large quantity of goods back home from the supermarket, he has to make multiple trips. While Xiao Hu, who has a private car, can transport more goods—which is much better than a motorcycle for cargo movement—he can only use specific bridges. If he just wants to buy water, the cost of driving increases. While he can also choose to walk, the efficiency will inevitably decrease. Therefore, the benefits and drawbacks of the Reduced and Complex Instruction Sets need to be determined based on the scene and demand.

In general, the Reduced Instruction Set is suitable for mobile applications due to its low energy consumption, power-saving capability, and somewhat lower performance. The Complex Instruction Set is appropriate for PCs as it processes quickly, and is more robust, but is quite bulky and sometimes not efficient enough. Of course, this is not absolute. In reality, both are learning from each other's strengths and weaknesses. For example, Apple's self-developed M series chip, is energy-efficient yet highly powerful.

Advantages of RISC-V

RISC-V and ARM share the same roots, but since ARM's ecosystem is already so strong, why are many developers opting for RISC-V, making it the third major CPU architecture?

Here are several main reasons

• Simplicity: In a 2019 comparison of several major instruction set manuals, RISC-V only had 236 pages and 76,702 words. In contrast, both ARM-32 and X86-32 amounted to over 2,000 pages, with X86-32 exceeding two million words. Simple generally implies more efficient and reliable.
• Low entry barrier, simple design: When ARM and X86 define new architectures, they must maintain compatibility with existing technologies, making their specification documents and the number of instructions complex and obscure—a high entry barrier for beginners. On the other hand, they unquestionably have a dominant advantage in terms of ecosystem. As a new architecture, RISC-V doesn't have to worry about this and is more user-friendly for designers. Its simpler design also means that as a Reduced Instruction Set, it can achieve the same performance on half the area.
• Portability, universality: The designers of RISC-V believe that a well-designed instruction set should be open-source and usable by anyone. Therefore, CPUs of the RISC-V architecture can be adapted to specific scenarios and choose suitable open-source architectures.
• Cost factors: This is the most important reason. Many are not well acquainted with ARM and believe that this architecture, which has ties with Apple, MediaTek, Qualcomm, Huawei, Kirin, is open source—this is not actually true. It's commercially licensed, and IP involves fees. ARM's charging items include initial licensing, royalties, and technical consulting service fees. Worth mentioning is that at the beginning of 2023, ARM once had the idea of changing its licensing model, where it intended to extract funds based on the price of the sold devices. This encountered strong collective protest from smartphone manufacturers as it would significantly increase their costs.

Conclusion

As a latecomer technology, RISC-V learns from the experiences of its predecessors, achieves relative simplicity and efficiency, openly embraces open source, and is very friendly for smaller companies.

Although its ecosystem is not yet mature, it has massive developmental potential. Currently, in areas like embedded systems and IoT, RISC-V is making steady progress thanks to its power efficiency.

The emergence of an open-source RISC-V will undoubtedly draw more players into the field. However, with more players, the risk of excessive liberalization increases, potentially leading to situations where these players establish their own standards based on existing foundations, develop core technologies independently, and become incompatible with each other. Therefore, RISC-V needs to prevent excessive IP fragmentation; otherwise, MIPS can serve as a cautionary tale for it in several aspects.

Moreover, if RISC-V becomes widely prevalent, the APIs being called will increase, and the instruction set may be further customized by some manufacturers. Due to compatibility considerations, the old underlying instruction set cannot be discarded. Therefore, whether it can maintain such high openness in the future and whether it would follow the same path as ARM remains to be seen.

Of course, solutions do exist—RISC-V needs some high-end players to jointly establish a common standard, such as standardizing the instruction set in a way that convinces everyone, thereby avoiding excessive fragmentation. High-end players can also leverage their influence and financial power to drive the construction of the software ecosystem, develop a large number of software tools, or even directly design related high-end hardware to seize the market of CPU core technologies. What RISC-V currently lacks the most is such a blockbuster product.

But new problems arise. As giants rush in and the suction effect emerges, everyone is not a philanthropist, and more people mean more opinions. Therefore, the say of the original founders of RISC-V may be further diluted. Those who enter the field will try to establish a long-term stable business model, while the founders might just have wanted to develop a completely open-source, patent-unhindered new instruction set architecture serving various industries. Can the future RISC-V remain true to its original intentions under the balance of multi-party interests? Of course, these are long-term concerns. The most immediate goal of RISC-V now is to survive—live first, then think about making money. Its first threat is to the ARM market, and we might soon have the opportunity to use a brand-new CPU architecture. As consumers, having more choices is always more interesting than the current sluggish and slow-progressing market, isn't it?

Reference

https://itmanabi.com/cisc-risc/

https://www.linkedin.com/pulse/risc-v-powered-disruption-semiconductor-smart-devices-/?trk=organization-update-content_share-article

https://circuitdigest.com/article/understanding-risc-v-architecture-and-why-it-could-be-a-replacement-for-ar